View ADP2116_4954604.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
ADP2116
FEATURES
Configurable 3 A/3 A or 3 A/2 A dual-output load combinations or 6 A combined single-output load High efficiency: up to 95% Input voltage, VIN: 2.75 V to 5.5 V Selectable fixed output voltage of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, or adjustable output voltage to 0.6 V minimum 1.5% accurate reference voltage Selectable switching frequency of 300 kHz, 600 kHz, 1.2 MHz, or synchronized from 200 kHz to 2 MHz Optimized gate slew rate for reduced EMI External synchronization input or internal clock output Dual-phase, 180 phase-shifted PWM channels Current mode for fast transient response Pulse skip mode with light loads or forced PWM operation Input undervoltage lockout (UVLO) Independent enable inputs and power-good outputs Overcurrent and thermal overload protection Programmable soft start 32-lead, 5 mm x 5 mm LFCSP package
TYPICAL APPLICATION CIRCUIT
VIN = 5V 10 100k 1F
OPCFG VDD
100k EN1 VIN1 VIN2 PGOOD1 3.3H VOUT1 = 2.5V, 3A 47F 22F
EN2 22F PGOOD2 VOUT2 = 1.2V, 3A 47F 100F 2.2H VIN4 VIN5 VIN6 PGOOD2 SW3 SW4 PGND3 PGND4 FB2 V2SET
22F
VIN3 PGOOD1 SW1
ADP2116 SW2
PGND1 PGND2 FB1 V1SET 27k
SYNC
4.7k
FREQ
30k 820pF
10nF
SCFG GND
SYNC/CLKOUT COMP1 COMP2 SS1 SS2
10nF
30k 820pF
8.2k
fSW = 600kHz
Figure 1.
100 VIN = 5.0V; VOUT = 2.5V 95 90
EFFICIENCY (%)
APPLICATIONS
Point-of-load regulation Telecommunications and networking systems Consumer electronics Industrial and instrumentation Medical
VIN = 5.0V; VOUT = 3.3V
85 80 75 70 65 VIN = 3.3V; VOUT = 1.2V
GENERAL DESCRIPTION
The ADP2116 is a versatile, synchronous, step-down switching regulator that satisfies a wide range of customer point-of-load requirements. The two PWM channels can be configured to deliver independent outputs at 3 A and 3 A (or at 3 A and 2 A) or can be configured as a single interleaved output capable of delivering 6 A. The two PWM channels are 180 phase shifted to reduce input ripple current and input capacitance. The ADP2116 provides high efficiency and can operate at switching frequencies of up to 2 MHz. At light loads, the ADP2116 can be set to operate in pulse skip mode for higher efficiency or in forced PWM mode for noise sensitive applications. The ADP2116 is designed with an optimized slew rate to reduce EMI emissions, allowing the device to power sensitive, high performance signal chain circuits. The switching frequency can be set to 300 kHz, 600 kHz, or 1.2 MHz, or it can be synchronized to an external clock that minimizes the system noise. The bidirectional
fSW = 600kHz
100 1k 10k LOAD CURRENT (mA)
08436-002
60 10
Figure 2. Typical Efficiency vs. Load Current
synchronization pin is also configurable as a 90 out-of-phase output clock, providing the possibility for a stackable multiphase power solution. The ADP2116 input voltage range is from 2.75 V to 5.5 V and can convert to a fixed output of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V that can be set independently for each channel using external resistors. If a resistor divider is used, the output voltage can be set as low as 0.6 V. The ADP2116 operates over the -40C to +125C junction temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
08436-001
ADP2116 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 8 Line and Load Regulation ........................................................... 9 Supply Current ............................................................................ 13 Load Transient Response........................................................... 14 Basic Functionality ..................................................................... 15 Bode Plots .................................................................................... 18 Simplified Block Diagram ............................................................. 19 Theory of Operation ...................................................................... 20 Control Architecture .................................................................. 20 Undervoltage Lockout (UVLO) ............................................... 20 Enable/Disable Control ............................................................. 20 Soft Start ...................................................................................... 20 Power Good................................................................................. 21 Pulse Skip Mode ......................................................................... 21 Hiccup Mode Current Limit ..................................................... 22 Thermal Overload Protection .................................................. 22 Maximum Duty Cycle Operation ............................................ 22 Synchronization .......................................................................... 22 Converter Configuration ............................................................... 23 Selecting the Output Voltage .................................................... 23 Setting the Oscillator Frequency .............................................. 24 Synchronization and CLKOUT ................................................ 24 Operation Mode Configuration ............................................... 25 External Components Selection ................................................... 26 Input Capacitor Selection .......................................................... 26 VDD RC Filter ............................................................................ 26 Inductor Selection ...................................................................... 26 Output Capacitor Selection....................................................... 27 Control Loop Compensation .................................................... 28 Design Example .............................................................................. 29 Channel 1 Configuration and Components Selection .......... 29 Channel 2 Configuration and Components Selection .......... 30 System Configuration ................................................................ 31 Application Circuits ....................................................................... 32 Power Dissipation and Thermal Considerations ....................... 34 Circuit Board Layout Recommendations ................................... 35 Outline Dimensions ....................................................................... 36 Ordering Guide .......................................................................... 36
REVISION HISTORY
10/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADP2116 SPECIFICATIONS
If unspecified, VDD = VINx = EN1 = EN2 = 5.0 V. The minimum and maximum specifications are valid for TJ = -40C to +125C, unless otherwise specified. Typical values are at TJ = 25C. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Table 1.
Parameter POWER SUPPLY VDD Bias Voltage Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Quiescent Current Symbol VDD UVLO Conditions Min 2.75 VDD rising VDD falling EN1 = VDD = 5 V, EN2 = GND, VFB1 = VDD, OPCFG = GND EN2 = VDD = 5 V, EN1 = GND, VFB2 = VDD, OPCFG = GND EN1 = EN2 = VDD = 5 V, VFB2 = VFB1 = VDD, OPCFG = GND EN1 = EN2 = GND, VDD = VINx = 2.75 V to 5.5 V, TJ = -40C to +115C 2.35 2.65 2.47 0.18 1.7 1.7 3.0 1.0 Typ Max 5.5 2.75 Unit V V V mA mA mA A
IDD,CH1 IDD,CH2 IDD,CH1 + CH2
2.5 2.5 4.0 10
Shutdown Current ERROR INTEGRATOR (OPERATIONAL TRANSCONDUCTANCE AMPLIFIER) FB1, FB2 Input Bias Current
IDD,SD
IFB
Adjustable output, VFBx = 0.6 V, V1SET, V2SET = VDD or via 82 k to GND Fixed output, VFBx = 1.2 V, V1SET, V2SET via 4.7 k to GND
1 11 550
65 15
nA A A/V V V V V V %
Transconductance COMPx VOLTAGE RANGE COMPx Zero-Current Threshold COMPx Clamp High Voltage COMPx Clamp Low Voltage OUTPUT CHARACTERISTICS Output Voltage Accuracy
gm VCOMP, ZCT VCOMP, HI VCOMP, LO VFB Guaranteed by design VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 2.75 V to 5.5 V Adjustable output, TJ = 25C, V1SET, V2SET = VDD or via 82 k to GND Adjustable output, TJ = -40C to +125C, V1SET, V2SET = VDD or via 82 k to GND Fixed output, TJ = 25C, V1SET, V2SET = GND or via 4.7 k, 8.2 k, 15 k, 27 k, 47 k to GND Fixed output, TJ = -40C to +125C, V1SET, V2SET = GND or via 4.7 k, 8.2 k, 15 k, 27 k, 47 k to GND VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 2.75 V to 5.5 V All oscillator parameters provided for VDD = 2.75 V to 5.5 V FREQ tied to GND FREQ via 8.2 k to GND FREQ via 27 k to GND fSYNC = 2 x fSW FREQ tied to GND FREQ via 8.2 k to GND FREQ via 27 k to GND
0.65 0.597 0.594 -1.0
1.12 2.36 0.70 0.600 0.600
2.45
0.603 0.606 +1.0
VFB ERROR
-1.5
+1.5
%
Line Regulation Load Regulation OSCILLATOR Switching Frequency fSW
0.05 0.03
%/V %/A
255 510 1020 400 800 1600 100
300 600 1200
345 690 1380 1000 2000 4000
kHz kHz kHz kHz kHz kHz ns
SYNC Frequency Range
fSYNC
SYNC Input Pulse Width
Rev. 0 | Page 3 of 36
ADP2116
Parameter SYNC Pin Capacitance to GND SYNC Input Logic Low SYNC Input Logic High Phase Shift Between Channels CLKOUT Frequency Symbol CSYNC VIL_SYNC VIH_SYNC fCLKOUT Conditions Min Typ 5 Max 0.8 2.0 180 fCLKOUT = 2 x fSW FREQ tied to GND FREQ via 8.2 k to GND FREQ via 27 k to GND CCLKOUT = 20 pF All current-limit parameters provided for VDD = VINx = 2.75 V to 5.5 V OPCFG tied to VDD or via 82 k to GND OPCFG tied to VDD or via 82 k to GND OPCFG via 47 k or 27 k to GND fSW = 300 kHz 510 1020 2040 100 600 1200 2400 10 690 1380 2760 Unit pF V V Degrees kHz kHz kHz ns ns
CLKOUT Positive Pulse Time CLKOUT Rise or Fall Time CURRENT LIMIT Peak Output Current Limit, Channel 1 Peak Output Current Limit, Channel 2 Current-Sense Amplifier Gain Hiccup Time Number of Cumulative Current-Limit Cycles to Go into Hiccup Mode SWITCH NODE CHARACTERISTICS High-Side, P-Channel RDSON 1 Low-Side, N-Channel RDSON1 SWx Minimum On Time SWx Minimum Off Time SWx Maximum Leakage Current ENABLE INPUTS EN1, EN2 Logic Low Level EN1, EN2 Logic High Level EN1, EN2 Input Leakage Current THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis SOFT START SS1, SS2 Pin Current Soft Start Threshold Voltage Soft Start Pull-Down Current POWER GOOD Overvoltage PGOODx Rising Threshold 2 Overvoltage PGOODx Falling Threshold2 Undervoltage PGOODx Rising Threshold2 Undervoltage PGOODx Falling Threshold2 PGOODx Delay PGOODx Leakage Current PGOODx Low Saturation Voltage
1 2
tCLKOUT
ILIMIT1 ILIMIT2 GCS
3.5 3.5 2.4 10
4.5 4.5 3.3 4 13.6 8
5.3 5.3 4.0 17
A A A A/V ms Cycles
SWON MIN SWOFF MIN
VDD = VINx = 3.3 V VDD = VINx = 5.0 V VDD = VINx = 3.3 V VDD = VINx = 5.0 V VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 5.5 V VDD = VINx = 2.75 V VDD = VINx = 2.75 V to 5.5 V, ENx = GND, TJ = -40C to +115C VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 2.75 V to 5.5 V VDD = VINx = ENx = 2.75 V to 5.5 V, TJ = -40C to +115C
68 52 32 27 107 192 255 0.1
15
m m m m ns ns ns A
ENLO ENHI IEN_LEAK
0.8 2.0 0.1 1
V V A
TTMSD
150 25 VDD = VINx = 2.75 V to 5.5 V, VSS = 0 V VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 2.75 V to 5.5 V, EN = GND All power-good parameters provided for VDD = VINx = 2.75 V to 5.5 V 4.8 0.5 6.0 0.65 7.8
C C A V mA
ISS1, ISS2 VSS_THRESH
100 85
VPGOODx = VDD IPGOODx = 1 mA
116 108 92 84 50 0.1 50
114 97
1 110
% % % % s A mV
Pin-to-pin measurements. The thresholds are expressed as a percentage of the nominal output voltage. Rev. 0 | Page 4 of 36
ADP2116 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VDD to GND VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to PGND1, PGND2, PGND3, PGND4 EN1, EN2, SCFG, FREQ, SYNC/CLKOUT, PGOOD1, PGOOD2, V1SET, V2SET, COMP1, COMP2, SS1, SS2 to GND FB1, FB2 to GND SW1, SW2, SW3, SW4 to PGND1, PGND2, PGND3, PGND4 PGND1, PGND2, PGND3, PGND4 to GND VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to VDD JA, JEDEC 1S2P PCB, Natural Convection Operating Junction Temperature Range Storage Temperature Range Maximum Soldering Lead Temperature (10 sec) Rating -0.3 V to +6 V -0.3 V to +6 V -0.3 V to (VDD + 0.3 V)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination.
-0.3 V to +3.6 V -0.3 V to (VDD + 0.3 V) 0.3 V 0.3 V 34C/W -40C to +125C -65C to +150C 260C
ESD CAUTION
Rev. 0 | Page 5 of 36
ADP2116 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FB1 V1SET SS1 PGOOD1 EN1 VIN1 VIN2 VIN3 32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
GND COMP1 FREQ SCFG SYNC/CLKOUT OPCFG COMP2 VDD
1 2 3 4 5 6 7 8
ADP2116
TOP VIEW (Not to Scale)
THERMAL PAD
SW1 SW2 PGND1 PGND2 PGND3 PGND4 SW3 SW4
FB2 V2SET SS2 PGOOD2 EN2 VIN4 VIN5 VIN6
9 10 11 12 13 14 15 16
NOTES 1. CONNECT THE EXPOSED THERMAL PAD TO THE SIGNAL/ANALOG GROUND PLANE.
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 Mnemonic GND COMP1 FREQ SCFG SYNC/CLKOUT Description Ground for the Internal Analog and Digital Circuits. Connect GND to the signal/analog ground plane before connecting to the power ground. Error Amplifier Output for Channel 1. Connect a series RC network from COMP1 to GND to compensate the control loop of Channel 1. For multiphase operation, tie COMP1 and COMP2 together. Frequency Select Input. Connect this pin through a resistor to GND to set the appropriate switching frequency (see Table 5). Synchronization Configuration Input. SCFG configures the SYNC/CLKOUT pin as an input or output. Tie this pin to VDD to configure SYNC/CLKOUT as an output. Tie this pin to GND to configure SYNC/CLKOUT as an input. External Synchronization Input/Internal Clock Output. This bidirectional pin is configured with the SCFG pin (see the Pin 4 description for details). When this pin is configured as an output, a buffered clock of twice the switching frequency with a phase shift of 90 is available on this pin. When configured as an input, this pin accepts an external clock to which the converters are synchronized. The frequency select resistor, mentioned in the description of Pin 3, must be selected to be close to the expected switching frequency for stable operation (see the Setting the Oscillator Frequency section). Operation Configuration Input. Connect this pin to VDD or through a resistor to GND to set the system mode of operation according to Table 7. This pin can be used to select a peak current limit for each power channel and to enable or disable the pulse skip mode. Error Amplifier Output for Channel 2. Connect a series RC network from COMP2 to GND to compensate the control loop of Channel 2. For multiphase operation, tie COMP1 and COMP2 together. Power Supply Input. The power source for the ADP2116 internal circuitry. Connect VDD and VINx with a 10 resistor as close as possible to the ADP2116. Bypass VDD to GND with a 1 F or greater capacitor. Feedback Voltage Input for Channel 2. For the fixed output voltage option, connect FB2 to VOUT2. For the adjustable output voltage option, connect this pin to a resistor divider between VOUT2 and GND. The reference voltage for the adjustable output voltage option is 0.6 V. With multiphase configurations, the FB2 and FB1 pins should be tied together and then connected to VOUT. Output Voltage Set Pin for Channel 2. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V) for VOUT2, connect this pin through a resistor to GND (see Table 4 for details). To select an adjustable output voltage for VOUT2, connect this pin to GND through an 82 k resistor or tie this pin directly to VDD depending on the output voltage desired. Soft Start Input for Channel 2. Place a capacitor from SS2 to GND to set the soft start period. A 10 nF capacitor sets a 1 ms soft start period. For multiphase configuration, connect SS2 to SS1. Open-Drain Power-Good Output for Channel 2. Place a 100 k pull-up resistor to VDD or to any other voltage that is 5.5 V or less; PGOOD2 is held low when Channel 2 is out of regulation. Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 converter; drive EN2 low to turn off the Channel 2 converter. Tie EN2 to VDD for startup with VDD. When using a multiphase configuration, connect EN2 to EN1.
Rev. 0 | Page 6 of 36
6
OPCFG
7 8 9
COMP2 VDD FB2
10
V2SET
11 12 13
SS2 PGOOD2 EN2
08436-003
ADP2116
Pin No. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Mnemonic VIN4 VIN5 VIN6 SW4 SW3 PGND4 PGND3 PGND2 PGND1 SW2 SW1 VIN3 VIN2 VIN1 EN1 PGOOD1 SS1 V1SET Description Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2. Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage. Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2. Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage. Power Ground. The source of the low-side internal power MOSFET of Channel 2. Power Ground. The source of the low-side internal power MOSFET of Channel 2. Power Ground. The source of the low-side internal power MOSFET of Channel 1. Power Ground. The source of the low-side internal power MOSFET of Channel 1. Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1. Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage. Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1. Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage. Power Supply Input. The source of the high-side internal power MOSFET of Channel 1. Power Supply Input. The source of the high-side internal power MOSFET of Channel 1. Power Supply Input. The source of the high-side internal power MOSFET of Channel 1. Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 converter; drive EN1 low to turn off the Channel 1 converter. Tie EN1 to VDD for startup with VDD. When using a multiphase configuration, connect EN1 to EN2. Open-Drain Power-Good Output for Channel 1. Place a 100 k pull-up resistor to VDD or to any other voltage that is 5.5 V or less; PGOOD1 is held low when Channel 1 is out of regulation. Soft Start Input for Channel 1. Place a capacitor from SS1 to GND to set the soft start period. A 10 nF capacitor sets a 1 ms soft start period. For multiphase configuration, connect SS1 to SS2. Output Voltage Set Pin for Channel 1. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V) for VOUT1, connect this pin through a resistor to GND (see Table 4 for details). To select an adjustable output voltage for VOUT1, connect this pin to GND through an 82 k resistor or tie this pin directly to VDD depending on the output voltage desired. Feedback Voltage Input for Channel 1. For the fixed output voltage option, connect FB1 to VOUT1. For the adjustable output voltage option, connect this pin to a resistor divider between VOUT1 and GND. With multiphase configurations, the FB1 and FB2 pins should be tied together and then connected to VOUT. Exposed Thermal Pad. Connect the exposed thermal pad to the signal/analog ground plane.
32
FB1
EP
Rev. 0 | Page 7 of 36
ADP2116 TYPICAL PERFORMANCE CHARACTERISTICS
100 95 90
EFFICIENCY (%)
95 90 85
85 80 75 70 65 60 10
EFFICIENCY (%)
80 75 70 65 60 55 10 VIN = 5V, PULSE SKIP VIN = 5V, FORCED PWM VIN = 3.3V, PULSE SKIP VIN = 3.3V, FORCED PWM 100 1k 10k
08436-006
08436-007
VOUT = 3.3V VOUT = 3.3V, PULSE SKIP VOUT = 1.8V VOUT = 1.8V, PULSE SKIP 100 1k 10k
08436-004
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 4. Efficiency vs. Load, VIN = 5 V and fSW = 300 kHz; VOUT = 3.3 V, Inductor Cooper Bussmann DR1050-8R2-R, 8.2 H, 15 m; VOUT = 1.8 V, Inductor TOKO FDV0620-4R7M, 4.7 H, 53 m
Figure 6. Efficiency vs. Load, VOUT = 1.2 V and fSW = 1.2 MHz; Inductor TOKO FDV0620-1R0M, 1.0 H, 14 m
100 95 90
EFFICIENCY (%)
EFFICIENCY (%)
95 90 85 80
VIN = 3.3V
85 80 75 70 65 60 10 VOUT = 2.5V, VOUT = 2.5V, VOUT = 1.2V, VOUT = 1.2V, 100 1k PULSE SKIP FORCED PWM PULSE SKIP FORCED PWM
08436-005
VIN = 5V
75 70 65 60 55 100
10k
1k LOAD CURRENT (mA)
10k
LOAD CURRENT (mA)
Figure 5. Efficiency vs. Load, VIN = 5 V and fSW = 600 kHz; VOUT = 2.5 V, Inductor TOKO FDV0620-3R3M, 3.3 H, 40 m; VOUT = 1.2 V, Inductor TOKO FDV0620-2R2M, 2.2 H, 30 m
Figure 7. Efficiency, Combined Dual-Phase Output, VOUT = 1.2 V and fSW = 1.2 MHz; Inductor TOKO FDV0620-1R0M, 1.0 H, 14 m
Rev. 0 | Page 8 of 36
ADP2116
LINE AND LOAD REGULATION
0.25 0.20
VOUT1 ERROR, NORMALIZED (%)
0.25 0.20
0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20
08436-008
VOUT2 ERROR, NORMALIZED (%)
0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 8. Load Regulation, Channel 1: VIN = 5 V, fSW = 600 kHz, and TA = 25C
Figure 11. Load Regulation, Channel 2: VIN = 5 V, fSW = 600 kHz, and TA = 25C
0.5 0.4
VOUT1 ERROR, NORMALIZED (%)
0.5 0.4
VOUT2 ERROR, NORMALIZED (%)
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
08436-009
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5
08436-012 08436-013
-0.5 3.5
4.0
4.5 VIN (V)
5.0
5.5
-0.5 2.5
Figure 9. Line Regulation, Channel 1: Load Current = 3 A and fSW = 600 kHz
Figure 12. Line Regulation, Channel 2: Load Current = 3 A and fSW = 600 kHz
1.00 0.75 0.50
1.00 0.75 0.50
VOUT1 ERROR (%)
0.25 VIN = 5.5V, NO LOAD 0 -0.25 -0.50 -0.75 -1.00 -50 VIN = 2.75V, 3A LOAD
VOUT2 ERROR (%)
0.25 VIN = 5.5V, NO LOAD 0 -0.25 -0.50 -0.75 -1.00 -50 VIN = 2.75V, 2A LOAD
-25
0
25
50
75
100
125
08436-010
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 10. Output Voltage Error vs. Temperature, Channel 1: VOUT = 0.6 V and fSW = 600 kHz
Figure 13. Output Voltage Error vs. Temperature, Channel 2: VOUT = 1.5 V and fSW = 600 kHz
Rev. 0 | Page 9 of 36
08436-011
-0.25
-0.25
ADP2116
250 225 200
330
fSW = 300kHz fSW = 600kHz fSW = 1.2MHz
320
MINIMUM ON TIME (ns)
310
175
fSW (kHz)
150 125
300
290
100
280
75 50 2.5
08436-014
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
VIN (V)
Figure 14. Minimum On Time, Open Loop, Includes Dead Time
Figure 17. Switching Frequency vs. Input Voltage, fSW = 300 kHz
350 330 310
660
fSW = 300kHz fSW = 600kHz fSW = 1.2MHz
640
MINIMUM OFF TIME (ns)
290
620
250 230 210 190 170
fSW (kHz)
270
600
580
560
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
08436-015
VIN (V)
Figure 15. Minimum Off Time, Open Loop, Includes Dead Time
Figure 18. Switching Frequency vs. Input Voltage, fSW = 600 kHz
120 +125C +115C +85C +25C -40C NMOS RDSON (m)
50 45 40 35 30 25 20 15 10 5
08436-016
100
+125C +115C +85C +25C -40C
PMOS RDSON (m)
80
60
40
20
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
Figure 16. High-Side PMOS Resistance vs. Input Voltage, Includes Bond Wires
Figure 19. Low-Side NMOS Resistance vs. Input Voltage, Includes Bond Wires
Rev. 0 | Page 10 of 36
08436-019
0 2.5
0 2.5
08436-018
150 2.5
540
2.5
3.0
3.5
4.0
4.5
5.0
5.5
08436-017
270 2.5
3.0
3.5
4.0
4.5
5.0
5.5
ADP2116
330 2.0 1.9 320
ENABLE/DISABLE THRESHOLD (V)
1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 ENABLE; VIN = 5.5V ENABLE; VIN = 2.75V DISABLE; VIN = 5.5V DISABLE; VIN = 2.75V
310
fSW (kHz)
VIN = 2.75V 300
VIN = 5.5V
290
280
08436-020
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 20. Switching Frequency vs. Temperature, fSW = 300 kHz
Figure 23. Enable/Disable Threshold vs. Temperature
660
2.8
640
UVLO THRESHOLD (V)
2.7
VDD RISING
620
VIN = 2.75V
fSW (kHz)
2.6
600 VIN = 5.5V 580
2.5
VDD FALLING
560
2.4
08436-021
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 21. Switching Frequency vs. Temperature, fSW = 600 kHz
Figure 24. UVLO Threshold vs. Temperature
1300 1280 1260 1240
1300 1280 1260 1240
VIN = 2.75V
fSW (kHz)
fSW (kHz)
1220 1200 1180 1160 1140 1120
08436-022
1220 1200
VIN = 5.5V
1180 1160 1140 1120
-25 0 25 50 75 100 125
08436-025
1100 2.5
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
1100 -50
TEMPERATURE (C)
Figure 22. Switching Frequency vs. Input Voltage, fSW = 1.2 MHz
Figure 25. Switching Frequency vs. Temperature, fSW = 1.2 MHz
Rev. 0 | Page 11 of 36
08436-024
540 -50
2.3 -50
08436-023
270 -50
0.8 -50
ADP2116
120 115 5.0 110
CURRENT LIMIT (A)
6.0 5.5
PGOOD1/PGOOD2 THRESHOLD (%)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0
3A OPTION
105 100 95 90 85 OVERVOLTAGE, VOUT RISING OVERVOLTAGE, VOUT FALLING UNDERVOLTAGE, VOUT RISING UNDERVOLTAGE, VOUT FALLING
2A OPTION
0.5
08436-026
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 26. PGOOD1/PGOOD2 Threshold vs. Temperature
Figure 29. Peak Current Limit vs. Temperature, VIN = 5 V
10 9 8
SHUTDOWN CURRENT (A)
700 650 600
7
gm (A/V)
6 5 4 3 2 1
08436-027
550 VIN = 5.5V 500 VIN = 2.75V 450 VIN = 5.5V 400 VIN = 2.75V 350 300 -50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 27. Shutdown Current vs. Temperature
Figure 30. gm vs. Temperature
5
4
VDD INPUT CURRENT (mA)
3
VIN = 5.5V
2
VIN = 2.75V
1
-25
0
25
50
75
100
125
TEMPERATURE (C)
Figure 28. VDD Input Current vs. Temperature, Not Switching
08436-028
0 -50
Rev. 0 | Page 12 of 36
08436-030
0 -50
08436-029
80 -50
0 -50
ADP2116
SUPPLY CURRENT
5.0 4.5
5.0 4.5
VDD SUPPLY CURRENT (mA)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 2.5
VDD SUPPLY CURRENT (mA)
FORCED PWM 4.0 3.5 3.0 2.5 2.0 1.5 1.0 2.5 PULSE SKIP
FORCED PWM
PULSE SKIP
3.0
3.5
4.0 VDD VOLTAGE (V)
4.5
5.0
5.5
VDD VOLTAGE (V)
Figure 31. VDD Supply Current, No Load, Channel 1: VOUT1 = 1.5 V, Channel 2: Off, fSW = 1.2 MHz
Figure 33. VDD Supply Current, No Load, Channel 1: VOUT1 = 1.5 V, Channel 2: VOUT2 = 0.8 V, fSW = 1.2 MHz
5.0 4.5
5.0 4.5
VDD SUPPLY CURRENT (mA)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 2.5 PULSE SKIP FORCED PWM
VDD SUPPLY CURRENT (mA)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 -50 VDD VDD VDD VDD -25 0 25 50 = 2.75V, PULSE SKIP = 5.5V, PULSE SKIP = 2.75V, FORCED PWM = 5.5V, FORCED PWM 75 100 125
08436-034
3.0
3.5
4.0 VDD VOLTAGE (V)
4.5
5.0
5.5
08436-032
TEMPERATURE (C)
Figure 32. VDD Supply Current, No Load, Channel 2: VOUT2 = 0.8 V, Channel 1: Off, fSW = 1.2 MHz
Figure 34. VDD Supply Current vs. Temperature, Channel 1: VOUT1 = 1.5 V, Channel 2: VOUT2 = 0.8 V, fSW = 1.2 MHz
Rev. 0 | Page 13 of 36
08436-033
3.0
3.5
4.0
4.5
5.0
5.5
08436-031
ADP2116
LOAD TRANSIENT RESPONSE
VOUT1, AC
2
2
VOUT2, AC
IOUT2
IOUT1
4
4
SW1, SW2
3
SW3, SW4
1
CH3 5.0V BW CH2 100mV BW M400s 62.5MS/s A CH4 CH4 2.0A BW 16ns/pt
08436-035
2.16A
CH3 5V
B W
CH2 50mV BW M200s 125MS/s A CH4 CH4 2.0A BW 8ns/pt
2.16A
Figure 35. Load Transient Response in Pulse Skip Mode, Channel 1: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 2.5 V, fSW = 600 kHz (See Table 12 for the Circuit Details)
Figure 38. Load Transient Response in Pulse Skip Mode, Channel 2: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 1.2 V, fSW = 600 kHz (See Table 12 for the Circuit Details)
VOUT1, AC
2
2
VOUT2, AC
IOUT1
IOUT2
4
4
08436-036
CH2 200mV BW M400s 50MS/s BW 200ns/pt CH4 1.0A
A CH4
1.7A
CH2 50mV BW M200s 125MS/s CH4 1.0A BW 8ns/pt
A CH4
1.7A
Figure 36. Load Transient Response in Pulse Skip Mode, Channel 1: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 3.3 V, fSW = 300 kHz (See Table 12 for the Circuit Details)
Figure 39. Load Transient Response in Pulse Skip Mode, Channel 2: 0.3 A to 3 A Load Step, VIN = 3.3 V, VOUT = 1.2 V, fSW = 1.2 MHz (See Table 12 for the Circuit Details)
4
VOUT, AC
2
VOUT , AC
IOUT
IOUT
2 4
08436-037
CH2 2.0A CH4 200mV
M200s
B W
A CH2
3.2A
T 24.00%
CH2 50mV BW CH4 2.0A BW
M200s 125MS/s 8ns/pt
A CH4
1.68A
Figure 37. Load Transient Response in Forced PWM Mode, Combined Output: 0 A to 6 A Load Step, VIN = 5 V, VOUT = 3.3 V, fSW = 600 kHz (See Table 12 for the Circuit Details)
Figure 40. Load Transient Response in Forced PWM Mode, Combined Output: 0.6 A to 6 A Load Step, VIN = 5 V, VOUT = 1.2 V, fSW = 600 kHz (See Table 12 for the Circuit Details)
Rev. 0 | Page 14 of 36
08436-040
08436-039
08436-038
ADP2116
BASIC FUNCTIONALITY
VOUT, AC
2
1
EN1 SW VOUT1
2
3
4
SS1 INDUCTOR CURRENT SW1, SW2
4
08436-041
3
08436-044
08436-046 08436-045
CH3 2.0V
B W
B CH2 10mV W M4s 1.25GS/s A CH3 CH4 500mA BW IT 400ps/pt
4.32V
CH1 5.0V CH3 5.0V
B W B W
CH2 1.0V CH4 2.0V
B W B W
M1.0ms 10MS/s 100ns/pt
A CH1
2.4V
Figure 41. Pulse Skip Mode, 110 mA Load
Figure 44. Soft Start, Channel 1: VOUT = 1.8 V, CSS1 = 10 nF
VOUT, AC
2
EN1
1
SW
2
VOUT1
3
4
SS1
INDUCTOR CURRENT
SW1, SW2
4
08436-042
3
B CH2 20mV W M1s 1.25GS/s A CH3 CH3 2.0V BW CH4 500mA BW IT 100ps/pt
2.52V
CH1 5.0V BW CH2 1.0V CH3 5.0V BW CH4 500mV
B W B W
M200s 50MS/s 20.0ns/pt
A CH1
2.4V
Figure 42. Forced PWM Mode, CCM Operation, 200 mA Load, fSW = 600 kHz
Figure 45. Soft Start with Precharged Output
VOUT, AC
2
SW
INDUCTOR CURRENT
4
3
INDUCTOR CURRENT
2
VOUT2
4
3
B CH2 20mV W M1s 1.25MS/s A CH3 CH3 2V BW CH4 500mA BW IT 100ps/pt
SW3, SW4 CH2 1.0V BW M1.0ms 50MS/s A CH2 CH3 5.0V BW CH4 2.0A BW 20ns/pt 1.12V
4.32V
Figure 43. Pulse Skip Enabled, DCM Operation, 200 mA Load, fSW = 600 kHz
08436-043
Figure 46. Current Limit Entry, Channel 2: VOUT = 1.8 V, 2 A Configuration, fSW = 600 kHz
Rev. 0 | Page 15 of 36
ADP2116
EXTERNAL SYNC INDUCTOR CURRENT
1 4
CHANNEL 1 SW VOUT2
2 4
CHANNEL 2 SW
SW3, SW4
3
08436-047
3
CH3 5.0V
B W
CH2 1.0V BW M10.0s 1.25GS/s A CH2 CH4 2.0A BW IT 200ps/pt
1.12V
CH1 5.0V CH3 5.0V
B W B W
CH4 5.0V
B W
M1.0s 1.25GS/s IT 100ps/pt
A CH1
3.0V
Figure 47. Current Limit Entry (Zoomed In), Channel 2: VOUT2 = 1.8 V, 2 A Configuration, fSW = 600 kHz
Figure 50. External Synchronization, fSYNC = 1.5 MHz, fSW = 750 kHz
INDUCTOR CURRENT CHANNEL 1 SW
4 4
CHANNEL 2 SW
VOUT2
2
3
INTERNAL CLKOUT
SW3, SW4
3
08436-048
1
CH3 5.0V
B W
CH2 1.0V BW M2.0ms 5.0MS/s A CH4 CH4 2.0A BW 200ns/pt
1.72A
CH1 5.0V CH3 5.0V
B B
W W
CH4 5.0V
B W
M1.0s 1.25GS/s IT 100psns/pt
A CH4
3.0V
Figure 48. Hiccup Mode, fSW = 600 kHz, 6.8 ms Hiccup Cycle
Figure 51. Internal Clock Output, fSW = 600 kHz, fCLKOUT = 1.2 MHz
CHANNEL 1 SW
INDUCTOR CURRENT
4
CHANNEL 3 SW
1
VOUT2
2
2 3
CHANNEL 2 SW
4
SW3, SW4
3
08436-049
CHANNEL 4 SW
CH2 1.0V BW M2.0ms 1.25GS/s A CH2 CH3 5.0V BW CH4 2.0A BW IT 40ns/pt
1.12V
CH1 2.0V CH3 2.0V
B W B W
CH2 2.0V CH4 2.0V
B W B W
M1.0s 1.25GS/s IT 400ps/pt
A CH1
2.0V
Figure 49. Exiting Hiccup Mode, Channel 2: VOUT2 = 1.8 V, fSW = 600 kHz
Figure 52. 4-Channel Operation, Two ADP2116 Devices, One Device Synchronizes the Other, 90 Phase-Shifted Switch Nodes
Rev. 0 | Page 16 of 36
08436-052
08436-051
08436-050
ADP2116
PHASE 1 SW
EN1
1
1
PHASE 2 SW
VOUT1
2
4
PGOOD1
3
INDUCTOR CURRENT, PHASE 1
SS1
4
08436-053 B B W B W
2 3
INDUCTOR CURRENT, PHASE 2
08436-054
CH1 5.0V CH3 5.0V
W
CH2 1.0V CH4 1.0V
M1ms 25MS/s 40ns/pt
A CH1
2.2V
CH1 5.0V CH2 2.0A CH3 2.0A CH4 5.0V
M2.0s T 79.6%
A CH1
1.9V
Figure 53. Power-Good Signal
Figure 54. Combined Dual-Phase Output Operation, VOUT = 1.2 V, fSW = 300 kHz, 6 A Load
Rev. 0 | Page 17 of 36
ADP2116
BODE PLOTS
50 40 30 20
MAGNITUDE (dB)
120 96 72 PHASE 48
MAGNITUDE (dB) PHASE (Degrees)
50 40 30 20 10 0 -10 -20 -30 -40 -50 1k
M1 M2
120 96 72 PHASE 48 24 MAGNITUDE 0 -24 -48 -72 -96 -120 10k 100k FREQUENCY (Hz)
PHASE (Degrees)
08436-056
10 0 MAGNITUDE -10 -20 -30 -40 -50 1k
M1 M2
24 0 -24 -48 -72 -96 -120 10k 100k FREQUENCY (Hz)
FREQUENCY MAGNITUDE PHASE
08436-055
M1
M2
M2 - M1
M1
M2
M2 - M1
56.62kHz 0.029dB 55.02
220.20kHz -18.743dB -0.468
163.58kHz -18.772dB -55.494
FREQUENCY MAGNITUDE PHASE
46.12kHz -0.558dB 47.275
186.41kHz -20.906dB 0.065
140.29kHz -20.348dB -47.210
Figure 55. Magnitude and Phase vs. Frequency, VIN = 5 V, VOUT = 2.5 V, Load = 3 A, fSW = 600 kHz, Crossover Frequency (fCROSS) = 57 kHz, Phase Margin = 55 (See Table 12 for the Circuit Details)
Figure 56. Magnitude and Phase vs. Frequency, VIN = 5 V, VOUT = 1.2 V, Load = 3 A, fSW = 600 kHz, Crossover Frequency (fCROSS) = 46 kHz, Phase Margin = 47 (See Table 12 for the Circuit Details)
Rev. 0 | Page 18 of 36
ADP2116 SIMPLIFIED BLOCK DIAGRAM
VDD GND SCFG UVLO UVLO PGOOD1
FREQ OSC SYNC/CLKOUT
PHASE SHIFT
OSC_CH1 OSC_CH2 CLIM_CH1
0.7V
VFB1 VIN1 0.5V VIN2 VIN3
OPCFG
CURRENT LIMIT/ CONFIGURATION
CLIM_CH2 PULSE SKIP ENABLE
EN1 COMP1 UVLO V1SET FB1 VOUT SELECTOR VFB1 SS1 ISS = 6A - + + OSC_CH1 PULSE SKIP ENABLE OTSD
GATE CONTROL LOGIC AND MOSFET DRIVERS WITH ANTI-SHOOTTHROUGH PROTECTION
PMOS
SW1 SW2
NMOS
gm ERROR
AMPLIFIER
PGND1 PGND2 HICCUP TIMER
VREF = 0.6V
PWM COMPARATOR
VDD SLOPE COMPENSATION/ RAMP GENERATOR CLIM_CH1 - +
POWER STAGE
CURRENT-SENSE AMPLIFIER
CURRENTLIMIT COMPARATOR
CHANNEL 1
0.7V THERMAL SHUTDOWN OTSD
PGOOD2
VFB2 VIN4 0.5V VIN5 VIN6
EN2 COMP2 UVLO V2SET FB2 VOUT SELECTOR VFB2 SS2 ISS = 6A - + + OSC_CH2 PULSE SKIP ENABLE OTSD
GATE CONTROL LOGIC AND MOSFET DRIVERS WITH ANTI-SHOOTTHROUGH PROTECTION
PMOS
SW3 SW4
NMOS
gm ERROR
AMPLIFIER
PGND3 PGND4 HICCUP TIMER
VREF = 0.6V
PWM COMPARATOR
VDD SLOPE COMPENSATION/ RAMP GENERATOR CLIM_CH2 - +
POWER STAGE
CURRENT-SENSE AMPLIFIER
Figure 57. Simplified Block Diagram
Rev. 0 | Page 19 of 36
08436-057
CURRENTLIMIT COMPARATOR
CHANNEL 2
ADP2116 THEORY OF OPERATION
The ADP2116 is a high efficiency, dual, fixed switching frequency, synchronous, step-down dc-to-dc converter with flex mode architecture, which is the Analog Devices, Inc., proprietary version of peak current mode control architecture. The device operates over an input voltage range of 2.75 V to 5.5 V. Each output channel can provide an adjustable output as low as 0.6 V and deliver up to 3 A of load current. When the output channels are tied together, they operate 180 out of phase to deliver up to 6 A of load current. The integrated high-side, P-channel power MOSFET and the low-side, N-channel power MOSFET yield high efficiency at medium to heavy loads. Pulse skip mode is available for improved efficiency at light loads. With a high switching frequency (up to 2 MHz) and integrated power switches, the ADP2116 is optimized to deliver high performance in a small package for power management solutions. The ADP2116 also includes undervoltage lockout (UVLO) with hysteresis, soft start, and power good, as well as protection features such as output short-circuit protection and thermal shutdown. The output voltages, current limits, switching frequency, pulse skip operation, and soft start time are externally programmable with tiny resistors and capacitors. Control logic with the anti-shoot-through circuit monitors and adjusts the low-side and high-side driver outputs to ensure breakbefore-make switching. This monitoring and control prevents cross-conduction between the internal high-side, P-channel power MOSFET and the low-side, N-channel power MOSFET.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO threshold is 2.65 V when VDD is increasing and 2.47 V when VDD is decreasing. The 180 mV hysteresis prevents the converter from turning off and on repeatedly in response to changing load conditions during a slow voltage transition on VDD that is close to the 2.75 V minimum operational level.
ENABLE/DISABLE CONTROL
The EN1 and EN2 pins are used to independently enable or disable Channel 1 and Channel 2, respectively. Drive ENx high to turn on the corresponding channel of the ADP2116. Drive ENx low to turn off the corresponding channel of the ADP2116, reducing the input current to less than 1 A. To force a channel to start automatically when input power is applied, connect the corresponding ENx pin to VDD. When shut down, the ADP2116 channels discharge the soft start capacitor, causing a new soft start cycle every time the converters are reenabled.
CONTROL ARCHITECTURE
The ADP2116 consists of two step-down dc-to-dc converters that deliver regulated output voltages, VOUT1 and VOUT2 (see Figure 1), by modulating the duty cycle at which the internal high-side, P-channel power MOSFET and the low-side, N-channel power MOSFET are switched on and off. In steady-state operation, the output voltage VOUT1 or VOUT2 is sensed on the corresponding feedback pin, FB1 or FB2, and attenuated in proportion to the selected output voltage on the V1SET or V2SET pin. An error amplifier integrates the error between the feedback voltage and the reference voltage (VREF = 0.6 V) to generate an error voltage at the COMP1 or COMP2 pin. The valley inductor current is sensed by a current-sense amplifier when the low-side, N-channel MOSFET is on. An internal oscillator turns off the low-side, N-channel MOSFET and turns on the high-side, P-channel MOSFET at a fixed switching frequency. When the high-side, P-channel MOSFET is enabled, the valley inductor current information is added to an emulated ramp signal and compared to the error voltage by the PWM comparator. The output of the PWM comparator modulates the duty cycle by adjusting the trailing edge of the PWM pulse that switches the power devices. Slope compensation is programmed internally into the emulated ramp signal and automatically selected, depending on the input voltage, output voltage, and switching frequency. This prevents subharmonic oscillations for greater than 50% duty cycle operation.
SOFT START
The ADP2116 soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during startup. Soft start begins after the undervoltage lockout threshold is exceeded and an enable pin, EN1 or EN2, is pulled high to greater than 2.0 V. External capacitors to ground are required on both the SS1 and SS2 pins. Each regulating channel has its own soft start circuit. When the converter powers up and is enabled, the internal 6 A current source charges the external soft start capacitor, establishing a voltage ramp slope at the SS1 or SS2 pin, as shown in Figure 58. The soft start time ends when the soft start ramp voltage exceeds the internal reference of 0.6 V.
EN
1
VOUT
2
SS
4
SW
3
08436-058
CH1 5.0V CH3 5.0V
B B
W W
CH2 1.0V CH4 2.0V
B W B W
M1.0ms 100ns/pt
A CH1
2.4V
Figure 58. Soft Start
Rev. 0 | Page 20 of 36
ADP2116
The capacitance value of the soft start capacitor defines the soft start time, tSS, based on specified in Table 1. If the rising output voltage (VOUT1 or VOUT2) exceeds 116% of the target output voltage (VOUT1SET or VOUT2SET), the PGOOD1 or PGOOD2 pin is held low. The PGOOD1 or PGOOD2 pin continues to be held low until the falling output voltage returns to 108% of the target value. If the output voltage drops below 84% of the target output voltage, the corresponding PGOOD1 or PGOOD2 pin is held low. The PGOOD1 or PGOOD2 pin continues to be held low until the output voltage rises to within 92% of the target output voltage. The PGOOD1 or PGOOD2 pin is then released, signaling that the output voltage is within the power-good window. The power-good thresholds are shown in Figure 60. The PGOOD1 and PGOOD2 outputs also sink current if an overtemperature condition is detected. Use these outputs as logic power-good signals by connecting the pull-up resistor from PGOOD1 or PGOOD2 to VDD. If the power-good function is not used, the pins can be left floating.
VREF I SS = t SS CSS
where: VREF is the internal reference voltage, 0.6 V. ISS is the soft start current, 6 A. CSS is the soft start capacitor value.
(1)
If the output voltage, VOUT1 or VOUT2, is precharged prior to enabling Channel 1 or Channel 2, respectively, the control logic prevents inductor current reversal by keeping the power MOSFETs turned off until the soft start voltage ramp at SS1 or SS2 reaches the precharged output voltage on VFB1 or VFB2 (see Figure 59).
EN1
1
VOUT1
2
PULSE SKIP MODE
The ADP2116 has built-in pulse skip circuitry that turns on during light loads, switching only as necessary to maintain the output voltage within regulation. This allows the converter to maintain high efficiency during light load operation by reducing the switching losses. The pulse skip mode can be selected by configuring the OPCFG pin as indicated in Table 7. In pulse skip mode, when the output voltage dips below regulation, the ADP2116 enters PWM mode for a few oscillator cycles to increase the output voltage so that it is within regulation. During the wait time between bursts, both power switches are off, and the output capacitor supplies all of the load current. Because the output voltage dips and recovers occasionally, the output voltage ripple in this mode is larger than the ripple in the PWM mode of operation. If the converter is configured to operate in forced PWM mode (by selecting this configuration using the OPCFG pin), the device operates with a fixed switching frequency, even at light loads.
SS1
4
SW1, SW2
3
08436-059
CH1 5.0V CH3 5.0V
B W B W
CH2 1.0V BW M200s 50MS/s CH4 500mV BW 20ns/pt
A CH1
2.4V
Figure 59. Soft Start with a Precharged Output
POWER GOOD
The ADP2116 features open-drain power-good outputs (PGOOD1 and PGOOD2) that indicate when the converter output voltage is within regulation. The power-good signal transitions low immediately when the corresponding channel is disabled. The power-good circuitry monitors the output voltage on the FB1 or FB2 pin and compares it to the rising and falling thresholds
VOUT RISING 116%
VOUT FALLING
% OF VOUT SET
108% 100% 92% 84% 100%
UNDERVOLTAGE
POWER GOOD
OVERVOLTAGE
POWER GOOD
UNDERVOLTAGE
08436-060
PGOOD1/PGOOD2
Figure 60. PGOOD1/PGOOD2 Thresholds
Rev. 0 | Page 21 of 36
% OF VOUT SET
ADP2116
HICCUP MODE CURRENT LIMIT
The ADP2116 features a hiccup mode current-limit implementation. When the peak inductor current exceeds the preset current limit for more than eight consecutive clock cycles, the hiccup mode current-limit condition occurs. The channel then goes to sleep for 6.8 ms (at a 600 kHz switching frequency), which is enough time for the output to be discharged and the average power dissipation to be reduced. After the 6.8 ms elapses, the channel wakes up with a soft start period (see Figure 61). If the current-limit condition is subsequently triggered, the channel again goes to sleep and wakes up after 6.8 ms. The current limits for the two channels are programmed by configuring the OPCFG pin (see Table 7). For the 3 A/3 A option, the output current limit is set to 4.5 A per output. For the 3 A/2 A option, the current limits are set to 4.5 A and 3.3 A for VOUT1 and VOUT2, respectively.
MAXIMUM DUTY CYCLE OPERATION
As the input voltage drops and approaches the output voltage, the ADP2116 smoothly transitions to maximum duty cycle operation, with the low-side, N-channel MOSFET switched on for the minimum off time. In maximum duty cycle operation, the output voltage dips below regulation because the output voltage is the product of the input voltage and the maximum duty cycle limitation. The maximum duty cycle limit is a function of the switching frequency and the input voltage, as shown in Figure 64.
SYNCHRONIZATION
The ADP2116 can be synchronized to an external clock such that the two channels operate at a switching frequency that is half of the input synchronization clock. The SYNC/CLKOUT pin can be configured as an input SYNC pin or an output CLKOUT pin through the SCFG pin, as detailed in Table 6. Through the input SYNC pin, the ADP2116 can be synchronized to an external clock such that the two channels switch at half the external clock frequency and are 180 out of phase. Through the output CLKOUT pin, the ADP2116 provides an output clock that is twice the switching frequency of the channels and 90 out of phase. Therefore, a single ADP2116 configured for the CLKOUT option acts as the master converter and provides an external clock for all other dc-to-dc converters (including other ADP2116 devices). These other converters are configured as slaves that accept an external clock and synchronize to it. This clock distribution approach synchronizes all dc-to-dc converters in the system and prevents beat harmonics that can lead to EMI issues. The ADP2116 is optimized to power high performance signal chain circuits. The slew rate of the switch node is controlled by the size of the driver devices. Fast slewing of the switch node is desirable to minimize transition losses but can, in turn, lead to serious EMI issues due to parasitic inductance. To minimize EMI generation, the slew rate of the drivers is optimized such that the ADP2116 can match the performance of low dropout regulators in supplying sensitive signal chain circuits while also providing excellent power efficiency.
INDUCTOR CURRENT
4
VOUT
2
SW
3
CH2 1.0V BW M2ms 5MS/s CH3 5.0V BW CH4 2.0A BW 200ns/pt
A CH4
1.72A
Figure 61. Hiccup Mode
THERMAL OVERLOAD PROTECTION
The ADP2116 has an internal temperature sensor that monitors the junction temperature. High current going into the switches or a hot printed circuit board (PCB) can cause the junction temperature of the ADP2116 to rise rapidly. When the junction temperature reaches approximately 150C, the ADP2116 goes into thermal shutdown and the converter is turned off. When the junction temperature cools to less than 125C, the ADP2116 resumes normal operation after the soft start sequence.
08436-061
Rev. 0 | Page 22 of 36
ADP2116 CONVERTER CONFIGURATION
SELECTING THE OUTPUT VOLTAGE
To set the output voltage, VOUT1 or VOUT2, select one of the six fixed voltages, as shown in Table 4, by connecting the V1SET or V2SET pin to GND through a resistor of an appropriate value (see Figure 62). V1SET and V2SET set the voltage output levels for Channel 1 and Channel 2, respectively. The feedback pin, FB1 or FB2, should be directly connected to VOUT1 or VOUT2. Table 4. Output Voltage Programming
RV1SET 5% 0 to GND 4.7 k to GND 8.2 k to GND 15 k to GND 27 k to GND 47 k to GND 82 k to GND 0 to VDD VOUT1 (V) 0.8 1.2 1.5 1.8 2.5 3.3 0.6 to <1.6 (adjustable) 1.6 to 3.3 (adjustable) RV2SET 5% 0 to GND 4.7 k to GND 8.2 k to GND 15 k to GND 27 k to GND 47 k to GND 82 k to GND 0 to VDD VOUT2 (V) 0.8 1.2 1.5 1.8 2.5 3.3 0.6 to <1.6 (adjustable) 1.6 to 3.3 (adjustable)
To limit output voltage accuracy degradation due to feedback bias current to less than 0.05% (0.5% maximum), ensure that the divider string current is greater than 20 A. To calculate the desired resistor values, first determine the value of the bottom divider string resistor, R1, using the following equation: R1 = VREF/ISTRING where: VREF is the internal reference voltage, 0.6 V. ISTRING is the resistor divider string current. When R1 is determined, calculate the value of the top resistor, R2, using the following equation: (2)
V - VREF R2 = R1 OUT VREF
VIN RFREQ RV1SET / RV2SET
(3)
VDD FREQ
V1SET/ V2SET VINx
ADP2116
VOUT1/VOUT2 L
If the required output voltage, VOUT1 or VOUT2, is in the adjustable range, from 0.6 V to <1.6 V, connect V1SET or V2SET through an 82 k resistor to GND. For the adjustable output voltage range of 1.6 V to 3.3 V, tie V1SET or V2SET to VDD (see Table 4). The adjustable output voltage of the ADP2116 is externally set by a resistive voltage divider from the output voltage to the feedback pin (see Figure 63). The ratio of the resistive voltage divider sets the output voltage, whereas the absolute value of these resistors sets the divider string current. For lower divider string currents, the small 10 nA (100 nA maximum) feedback bias current should be taken into account when calculating the resistor values. The feedback bias current can be ignored for a higher divider string current; however, this degrades efficiency at very light loads.
SWx FB1/FB2 PGNDx COMP1/ COMP2
Figure 62. Configuration for Fixed Outputs
VIN RFREQ RV1SET / RV2SET
VDD FREQ
V1SET/ V2SET VINx
ADP2116
SWx FB1/FB2 PGNDx GND COMP1/ COMP2
L R2 R1
VOUT1/VOUT2
08436-062 08436-063
GND
Figure 63. Configuration for Adjustable Outputs
Rev. 0 | Page 23 of 36
ADP2116
SETTING THE OSCILLATOR FREQUENCY
The ADP2116 channels can be set to operate in one of three preset switching frequencies: 300 kHz, 600 kHz, or 1.2 MHz. For 300 kHz operation, connect the FREQ pin to GND. For 600 kHz or 1.2 MHz operation, connect a resistor between the FREQ pin and GND (see Table 5). Table 5. Oscillator Frequency Setting
RFREQ 5% 0 to GND 8.2 k to GND 27 k to GND fSW (kHz) 300 600 1200
irrespective of whether SYNC/CLKOUT is configured as an input or an output.
fSYNC (or fCLKOUT) = 2 x fSW
(4)
An external clock can be applied to the SYNC/CLKOUT pin when configured as an input to synchronize multiple ADP2116 devices to the same external clock. The fSYNC range is 400 kHz to 4 MHz, which produces fSW in the 200 kHz to 2 MHz range (see Figure 65).
VIN 27k 27k
SCFG
FREQ
VDD
SCFG
FREQ
VDD
SYNC (fSW = fSYNC /2)
SYNC (fSW = fSYNC /2)
The choice of the switching frequency depends on the required dcto-dc conversion ratio and the need for small external components. In addition, due to the minimum on and off times required for current sensing and robust operation, the frequency is limited by the minimum and maximum controllable duty cycle (see Figure 64).
100 90 80
DUTY CYCLE LIMITS (%)
ADP2116
fSYNC
EXTERNAL CLOCK (2.4MHz)
ADP2116
TO OTHER ADP2116 DEVICES
08436-065
08436-066
Figure 65. Synchronization with External Clock (fSW = 1.2 MHz)
When synchronizing to an external clock, the switching frequency (fSW) must be set close to half of the expected external clock frequency by appropriately terminating the FREQ pin (see Table 5). The ADP2116 can also be configured to output a clock signal on the SYNC/CLKOUT pin that can be used to synchronize multiple ADP2116 devices (see Figure 66). The CLKOUT signal is 90 phase shifted relative to the internal clock of the channels so that the master ADP2116 and the slave channels are out of phase (see Figure 67 for additional information).
VIN 8.2k 8.2k
70 60 50 40 30 20 10
08436-064
MAXIMUM LIMIT MINIMUM LIMIT, VIN = 2.75V MINIMUM LIMIT, VIN = 3.3V MINIMUM LIMIT, VIN = 5.5V
SCFG
FREQ
VDD
SCFG
FREQ
VDD
0 200
400
600
800
1000
1200
SYNC (fSW = fSYNC /2)
CLKOUT (fCLKOUT = 2 x fSW)
SWITCHING FREQUENCY (kHz)
ADP2116
fSYNC = 2 x fSW
TO OTHER ADP2116 DEVICES
ADP2116
Figure 64. Duty Cycle Working Limits
For small, area-limited power solutions, use of higher switching frequencies is recommended. For single-output, multiphase applications that operate at close to 50% duty cycle, use a 1.2 MHz switching frequency to minimize crosstalk between the phases.
Figure 66. ADP2116 to Synchronize with Another ADP2116 (fSW = 600 kHz; the SCFG Pin of the Master Is Tied to VDD)
SYNCHRONIZATION AND CLKOUT
The ADP2116 can be configured to output an internal clock or to synchronize to an external clock at the SYNC/CLKOUT pin. The SYNC/CLKOUT pin is a bidirectional pin configured by the SCFG pin (see Table 6). Table 6. SYNC/CLKOUT Configuration Setting
SCFG GND VDD SYNC/CLKOUT Input (SYNC) Output (CLKOUT)
4
CHANNEL 1 SW
CHANNEL 2 SW
3
INTERNAL CLKOUT
1
The converter switching frequency, fSW, is half of the synchronization frequency, fSYNC or fCLKOUT, as shown in Equation 4,
CH1 5.0V CH3 5.0V
B W B W
M1.0s CH4 5.0V
B W
A CH4
3.00V
Figure 67. CLKOUT Waveforms
Rev. 0 | Page 24 of 36
08436-067
ADP2116
OPERATION MODE CONFIGURATION
The dual-channel ADP2116 can be configured to one of four modes of operation by connecting the OPCFG pin as detailed in Table 7. The configuration sets the current limit for each channel and enables or disables the transition to pulse skip mode at light loads. In the dual-phase configuration, the outputs of the two channels are connected together and generate a single dc output voltage, VOUT. For this single combined dual-phase output, only Mode 1 (see Table 7) can be used. In this mode, the error amplifiers of both phases are used. The feedback pins (FB1 and FB2) are tied together, the compensation pins (COMP1 and COMP2) are tied together, the soft start pins (SS1 and SS2) are tied together, and the enable pins (EN1 and EN2) are tied together. In addition, if the power-good feature is used, PGOOD1 and PGOOD2 should be tied together and then connected to VDD using a single pull-up resistor. When the ADP2116 is synchronized to an external clock, the converters always operate in fixed-frequency CCM and do not enter pulse skip mode at light loads. In this case, when configuring the OPCFG pin, choose forced PWM mode.
Table 7. Current-Limit Operation Mode and Configuration
Mode 1 2 3 4 ROPCFG 5% 0 to VDD 82 k to GND 47 k to GND 27 k to GND Maximum Output Current, IOUT1 (A)/IOUT2 (A) 3/3 3/3 3/2 3/2 Peak Current Limit, ILIMIT1 (A)/ILIMIT2 (A) 4.5/4.5 4.5/4.5 4.5/3.3 4.5/3.3 Power Savings at Light Load Forced PWM Pulse skip enabled Forced PWM Pulse skip enabled
Rev. 0 | Page 25 of 36
ADP2116 EXTERNAL COMPONENTS SELECTION
INPUT CAPACITOR SELECTION
The input current to a buck converter is pulsating in nature. The current is zero when the high-side switch is off and approximately equal to the load current when the high-side switch is on. Because this pulsation occurs at reasonably high frequencies (300 kHz to 1.2 MHz), the input bypass capacitor supplies most of the high frequency current (ripple current), allowing the input power source to supply only the average (dc) current. The input capacitor needs a sufficient ripple current rating to handle the input ripple, as well as an ESR that is low enough to mitigate the input voltage ripple. For the ADP2116, place a 22 F, 6.3 V X5R ceramic capacitor close to the VINx pin for each channel. X5R or X7R dielectrics are recommended with a voltage rating of 6.3 V or 10 V. Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics. As a guideline, the inductor peak-to-peak current ripple, IL, is typically set to be one-third of the maximum load current for optimal transient response and efficiency.
I L = VOUT x (V IN - VOUT ) V IN x f SW x L I LOAD (MAX ) 3
L IDEAL =
3 x VOUT x (V IN - VOUT ) f SW x V IN x I LOAD ( MAX )
(5)
where: VIN is the input voltage on the VINx terminal. VOUT is the desired output voltage. fSW is the converter switching frequency. The internal slope compensation introduces additional limitations on the optimal inductor value for stable operation because the internal ramp is scaled for each VOUT setting. The limits for different VIN, VOUT, and fSW combinations are listed in Table 8.
Table 8. Minimum and Maximum Inductor Values
fSW (kHz) 300 300 300 300 300 300 300 300 300 300 300 600 600 600 600 600 600 600 600 600 600 600 1200 1200 1200 1200 1200 1200 1200 1200 1200 VIN (V) 5 5 3.3 5 3.3 5 3.3 5 3.3 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3 VOUT (V) 3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 1.2 0.8 0.8 3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 1.2 0.8 0.8 2.5 1.8 1.8 1.5 1.5 1.2 1.2 0.8 0.8 Min L (H) 6.8 5.6 5.6 4.7 4.7 2.2 2.2 2.2 2.2 1.5 1.5 3.3 3.3 3.3 2.2 2.2 1.5 1.5 1.5 1.5 1.0 1.0 1.0 1.0 1.0 0.8 0.8 0.8 0.8 0.47 0.47 Max L (H) 10 15 6.8 12 8.2 12 8.2 10 8.2 6.8 6.8 4.7 6.8 3.3 6.8 3.3 5.6 4.7 4.7 3.3 3.3 3.3 3.3 3.3 2.2 2.2 2.2 2.2 2.2 1.5 1.5
VDD RC FILTER
It is recommended that the input power, VIN, be apply to the VDD pin through a low-pass RC filter, as shown in Figure 68. Connecting a 10 resistor in series with VIN and a 1 F, 6.3 V X5R (or X7R) ceramic capacitor between VDD and GND creates a 16 kHz (-3 dB) low-pass filter that effectively attenuates voltage glitches on the input power rail caused by the switching regulator. This provides a clean power supply to the internal, sensitive analog and digital circuits in the ADP2116, ensuring robust operation.
VIN 10 VDD 1F
ADP2116
GND
08436-068
Figure 68. Low-Pass Filter at VDD
INDUCTOR SELECTION
The high switching frequency of the ADP2116 allows for minimal output voltage ripple even with small inductors. The size of the inductor is a trade-off between efficiency and transient response. A small inductor leads to larger inductor current ripple that provides excellent transient response but degrades efficiency. Due to the high switching frequency of the ADP2116, shielded ferrite core inductors are recommended for their low core losses and low EMI.
Rev. 0 | Page 26 of 36
ADP2116
To avoid saturation, the rated current of the inductor must be larger than the maximum peak inductor current, IL_PEAK, given by
I L _ PEAK = I LOAD _ MAX + I L 2 (6) If there is a step load, choose the output capacitor value based on the value of the step load. For the maximum acceptable output voltage droop/overshoot caused by the step load,
3 COUT_MIN I OUT_STEP x f x V DROOP SW
where: ILOAD_MAX is the maximum dc load current. IL is the peak-to-peak inductor ripple current. The ADP2116 can be configured in either a 3 A/3 A or 3 A/2 A current-limit configuration; therefore, the current-limit thresholds for the two channels are different in each setting. The inductor chosen for each channel must have at least the peak output current limit of the IC in each case for robust operation during short-circuit conditions. The following inductors are recommended:
* *
(9)
where: IOUT_STEP is the load step value in amperes. fSW is the switching frequency in hertz. VDROOP is the maximum allowable output voltage droop/overshoot in volts for the load step. Note that the previous equations are approximations and are based on the following assumptions:
* * *
For 0.47 H to 4.7 H, the TOKO D53LC and FDV0620 series inductors For 4.7 H to 15 H, the Cooper Bussmann DR1050 series and the Wurth Elektronik WE-PDF series
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. The ADP2116 is designed for operation with small ceramic output capacitors that have low ESR and low ESL and are, therefore, easily able to meet stringent output voltage ripple specifications. X5R or X7R dielectrics are recommended with a voltage rating of 6.3 V or 10 V. Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics. The minimum output capacitance, COUT_MIN, is determined by Equation 7 and Equation 8. An acceptable maximum output voltage ripple is
1 VRIPPLE I L x ESR + 8 x f SW x COUT_MIN
The inductor value is based on the peak-to-peak current being 30% of the maximum load current. Voltage drops across the internal MOSFET switches and across the dc resistance of the inductor are ignored. In Equation 9, it is assumed that it takes up to three switching cycles until the loop adjusts the inductor current in response to the load step.
Select the largest output capacitance given by Equation 8 and Equation 9. When choosing the type of ceramic capacitor for the output filter of the converter, select a capacitor with a nominal capacitance that is 20% to 30% larger than the calculated value because the effective capacitance decreases with larger dc voltages. In addition, the rated voltage of the capacitor must be higher than the output voltage of the converter. Recommended input and output ceramic capacitors include
* * * * *
(7)
Murata GRM21BR61A106KE19L, 10 F, 10 V, X5R, 0805 TDK C2012X5R0J226M, 22 F, 6.3 V, X5R, 0805 Taiyo Yuden JMK212BJ476MG-T, 47 F, 6.3 V, X5R, 0805 Murata GRM32ER60J476ME20L, 47 F, 6.3 V, X5R, 1210 Murata GRM32ER60J107ME20L, 100 F, 6.3 V, X5R, 1210
Therefore,
COUT_MIN I L 8 x f SW x (VRIPPLE -- I L x ESR)
(8)
where: VRIPPLE is the allowable peak-to-peak output voltage ripple in volts. IL is the inductor ripple current. ESR is the equivalent series resistance of the capacitor in ohms. fSW is the converter switching frequency in hertz.
Rev. 0 | Page 27 of 36
ADP2116
CONTROL LOOP COMPENSATION
The ADP2116 uses a peak current-mode control architecture for excellent load and line transient response. The external voltage loop is compensated by a transconductance amplifier with a simple external RC network between the COMP1 or COMP2 pin and GND, as shown in Figure 69.
ADP2116
VFBx COMPx RCOMP
ZCOMP(s) is the impedance of the RC compensation network that forms a pole at origin and a zero as expressed in Equation 13. ZCOMP(s) =
1 + s x RCOMP x CCOMP s x CCOMP
(13)
ZFILT(s) is the impedance of the output filter and is expressed as ZFILT(s) = RLOAD 1 + s x RLOAD x COUT (14)
gm
CCOMP 0.6V GND
where s is the angular frequency that can be written as s = 2f.
CC2
The overall loop gain, H(s), is obtained by multiplying the three transfer functions previously mentioned as follows:
08436-069
H(s) = gm x GCS x
Figure 69. Compensation Components
VREF x ZCOMP(s) x ZFILT(s) VOUT
(15)
The basic control loop block diagram is shown in Figure 70. The blocks and components shown enclosed within the dashed line in Figure 70 are embedded inside each channel of the ADP2116.
VIN INDUCTOR CURRENT SENSE PULSEWIDTH MODULATOR IL VOUT
When the switching frequency (fSW), output voltage (VOUT), output inductor (L), and output capacitor (COUT) values are selected, the unity crossover frequency of approximately 1/12 the switching frequency can be targeted. At the crossover frequency, the gain of the open-loop transfer function is unity. This yields Equation 16 for the compensation network impedance at the crossover frequency. ZCOMP ( fCROSS ) = 2 x x fCROSS x COUT VOUT x g m x GCS VREF (16)
VCOMP CCOMP RCOMP
gm
VREF = 0.6V
08436-070
ADP2116
To ensure that there is sufficient phase margin at the crossover frequency, set the compensator zero to 1/8 of the crossover frequency, as indicated in Equation 17. f ZERO = f 1 CROSS 2 x x RCOMP x CCOMP 8 (17)
Figure 70. Basic Control Loop Block Diagram
The control loop can be broken down into the following three sections:
* * *
VOUT to VCOMP VCOMP to IL IL to VOUT
Solving Equation 16 and Equation 17 yields the values for the compensation resistor and the compensation capacitor, as shown in Equation 18 and Equation 19.
(2 ) f CROSS R COMP = 0.9 x gG m CS C OUT VOUT x V REF
(18)
Correspondingly, there are three transfer functions:
VCOMP(s) VREF = x g m x ZCOMP(s) VOUT (s) VOUT I L(s) = GCS VCOMP(s) VOUT (s) = Z FILT (s) I L(s)
where: s is the angular frequency that can be written as s = 2f. gm is the transconductance of the error amplifier, 550 S. GCS is the current-sense gain, 4 A/V. VOUT is the output voltage of the converter. VREF is the internal reference voltage, 0.6 V. ZCOMP is the impedance of the RC compensation network. ZFILT is the impedance of the output filter.
CCOMP =
(10) (11) (12)
1 2 x x f ZERO x RCOMP
(19)
Capacitor CC2 (as shown in Figure 69) forms a pole with the compensation resistor, RCOMP, in the feedback loop to ensure that the loop gain continues to decrease, or roll off, well beyond the unity-gain crossover frequency. The value of CC2, if used, is typically set to 1/40 of the compensation capacitor, CCOMP.
Rev. 0 | Page 28 of 36
ADP2116 DESIGN EXAMPLE
The external component selection procedure from the Control Loop Compensation section is used for this design example.
Table 9. 2-Channel, Step-Down DC-to-DC Converter Requirements
Parameter Input Voltage, VIN Output Voltage for Channel 1, VOUT1 Output Voltage for Channel 2, VOUT2 Pulse Skip Feature Specification 5.0 V 10% 2.5 V, 3 A, 1% VOUT p-p ripple 1.2 V, 3 A, 1% VOUT p-p ripple Enabled Additional Requirements None Maximum load step: 1.5 A to 3 A, 5% droop maximum Maximum load step: 1.5 A to 3 A, 5% droop maximum None
the actual PCB footprint area of the converter will be larger because of the bigger inductor and output capacitors. 3. Select the inductor by using the following equation:
L= (V IN - VOUT ) VOUT x I L x f SW V IN
In this equation, VIN = 5 V, VOUT = 2.5 V, IL = 0.3 x IL = 0.9 A, and fSW = 600 kHz, which results in L = 2.32 H. Therefore, when L = 3.3 H (the closest minimum standard value from Table 8) in Equation 5, IL = 0.63 A. Although the maximum output current required is 3 A, the maximum peak current is 4.5 A for the current-limit condition (see Table 7). Therefore, the inductor should be rated for a peak current of 4.5 A and an average current of 3 A for reliable circuit operation. 4. Select the output capacitor by using the following equations:
C OUT_MIN I L 8 x f SW x (V RIPPLE - I L x ESR)
CHANNEL 1 CONFIGURATION AND COMPONENTS SELECTION
Complete the following steps to configure Channel 1: 1. For a target output voltage (VOUT) of 2.5 V, connect the V1SET pin through a 27 k resistor to GND (see Table 4). Because one of the fixed output voltage options is chosen, the feedback pin (FB1) must be connected directly to the output of Channel 1, VOUT1. Estimate the duty cycle (D) range. Ideally,
D= VOUT V IN
3 COUT_MIN IOUT_STEP x f x V DROOP SW

2.
(20)
Therefore, for an output voltage of 2.5 V and a nominal input voltage (VIN) of 5.0 V, the nominal duty cycle (DNOM) is 0.5. Using the maximum input voltage (10% greater than the nominal, or 5.5 V) results in the minimum duty cycle (DMIN) of 0.45, whereas using the minimum input voltage (10% less than the nominal, or 4.5 V) results in the maximum duty cycle (DMAX) of 0.56. However, the actual duty cycle will be larger than the calculated values to compensate for the power losses in the converter. Therefore, add 5% to 7% to the value calculated for the maximum load. Based on the estimated duty cycle range, choose the switching frequency (fSW) according to the minimum and maximum duty cycle limitations, as shown in Figure 64. If the input voltage (VIN) is 5 V and the output voltage (VOUT) is 2.5 V for Channel 1, choose a switching frequency of 600 kHz with a maximum duty cycle of 0.8. This frequency option provides the smallest sized solution. If a higher efficiency is required, choose the 300 kHz option. However,
The first equation is based on the output ripple (VRIPPLE), whereas the second equation is based on the transient load performance requirements that allow, in this case, 5% maximum deviation. As previously mentioned, perform these calculations and then choose a capacitor based on the larger calculated capacitor size. In this case, the following values are used: IL = 0.63 A fSW = 600 kHz VRIPPLE = 25 mV (1% of 2.5 V) ESR = 3 m (typical for ceramic capacitors) IOUT_STEP = 1.5 A VDROOP = 0.125 V (5% of 2.5 V) Therefore, the output ripple based calculation dictates that COUT = 6.2 F, whereas the transient load based calculation dictates that COUT = 60 F. To meet both requirements, use the larger capacitor value. As previously mentioned in the Output Capacitor Selection section, the capacitance value decreases when dc bias is applied; therefore, select a higher value. In this case, the next higher value is 69 F (a 47 F capacitor in parallel with 22 F) with a minimum voltage rating of 6.3 V.
Rev. 0 | Page 29 of 36
ADP2116
5. Calculate the compensation component values of the feedback loop by using the following equation:
(2 ) f CROSS R COMP = 0.9 x gG m CS C OUT VOUT x V REF
However, the actual duty cycle will be larger than the calculated values to compensate for the power losses in the converter. Therefore, add 5% to 7% to the value calculated for the maximum load. The switching frequency (fSW) of 600 kHz, which is chosen based on the Channel 1 requirements, meets the duty cycle ranges that were previously calculated. Therefore, this switching frequency is acceptable. 3. Select the inductor by using the following equation:
L= (VIN - VOUT ) VOUT x I L x f SW VIN
where: gm = 550 S. GCS = 4 A/V. VREF = 0.6 V. VOUT = 2.5 V. COUT = 0.8 x 69 F (capacitance derated by 20% to account for dc bias). Therefore, from Equation 18, RCOMP = 30 k. Substituting RCOMP in Equation 19 yields CCOMP = 820 pF.
Table 10. Channel 1 Circuit Settings
Circuit Parameter Output Voltage, VOUT Reference Voltage, VREF Error Amplifier Transconductance, gm Current-Sense Gain, GCS Switching Frequency, fSW Crossover Frequency, fCROSS Zero Frequency, fZERO Output Inductor, LOUT Output Capacitor, COUT Compensation Resistor, RCOMP Compensation Capacitor, CCOMP Setting See Step 1 Fixed, typical Fixed, typical Fixed, typical See Step 2 1/12 fSW 1/8 fCROSS See Step 3 See Step 4 See Equation 18 See Equation 19 Value 2.5 V 0.6 V 550 S 4 A/V 600 kHz 50 kHz 6.25 kHz 3.3 H (47 + 22) F 30 k 820 pF
In this equation, VIN = 5 V, VOUT = 1.2 V, IL = 0.3 x IL = 0.9 A, and fSW = 600 kHz, which results in L = 1.67 H. Therefore, when L = 2.2 H (the closest standard value) in Equation 5, IL = 0.69 A. Although the maximum output current required is 3 A, the maximum peak current is 4.5 A for the current-limit condition (see Table 7). Therefore, the inductor should be rated for a peak current of 4.5 A and an average current of 3 A for reliable circuit operation in all conditions. 4. Select the output capacitor by using the following equations:
COUT_MIN I L 8 x f SW x (VRIPPLE - I L x ESR)
3 COUT_MIN I OUT_STEP x f x V DROOP SW

CHANNEL 2 CONFIGURATION AND COMPONENTS SELECTION
Complete the following steps to configure Channel 2: 1. For a target output voltage (VOUT) of 1.2 V, connect the V2SET pin through a 4.7 k resistor to GND (see Table 4). Because one of the fixed output voltage options is chosen, the feedback pin (FB2) must be directly connected to the output of Channel 2, VOUT2. Estimate the duty cycle (D) range. Ideally,
D= VOUT V IN
The first equation is based on the output ripple (VRIPPLE), whereas the second equation is based on the transient load performance requirements that allow, in this case, 5% maximum deviation. As previously mentioned, perform these calculations and then choose a capacitor based on the larger calculated capacitor size. In this case, the following values are used: IL = 0.69 A fSW = 600 kHz VRIPPLE = 12 mV (1% of 1.2 V) ESR = 3 m (typical for ceramic capacitors) IOUT_STEP = 1.5 A VDROOP = 0.06 V (5% of 1.2 V) The output ripple based calculation dictates that COUT = 20 F, whereas the transient load based calculation dictates that COUT = 125 F. To meet both requirements, use the latter to choose a capacitor. As previously mentioned in the Output Capacitor Selection section, the capacitance value decreases when dc bias is applied; therefore, select a higher value. In this case, choose a 47 F, 6.3 V capacitor and a 100 F, 6.3 V capacitor in parallel to meet the requirements.
2.
Therefore, for an output voltage of 1.2 V and a nominal input voltage (VIN) of 5.0 V, the nominal duty cycle (DNOM) is 0.24. Using the maximum input voltage (10% greater than the nominal, or 5.5 V) results in the minimum duty cycle (DMIN) of 0.22, whereas using the minimum input voltage (10% less than the nominal, or 4.5 V) results in the maximum duty cycle (DMAX) of 0.27.
Rev. 0 | Page 30 of 36
ADP2116
5. Calculate the compensation component values of the feedback loop by using the following equation:
R COMP
SYSTEM CONFIGURATION
Complete the following steps to further configure the ADP2116 for this design example: 1. Set the switching frequency (fSW) to 600 kHz (see Table 5) by connecting the FREQ pin through an 8.2 k resistor to GND. Tie SCFG to VDD and use the CLKOUT signal to synchronize other converters on the same board with the ADP2116. Tie OPCFG through an 82 k resistor to GND for 3 A/3 A maximum output current operation and to enable pulse skip mode at light load conditions (see Table 7).
(2 ) f CROSS = 0.9 x gG m CS
C OUT VOUT x V REF

where: gm = 550 S. GCS = 4 A/V. VREF = 0.6 V. VOUT = 1.2 V. COUT = 0.8 x (47 + 100) F (capacitance derated by 20% to account for dc bias). From Equation 18,
2.
3.
RCOMP = 30 k.
Substituting RCOMP in Equation 19 yields CCOMP = 820 pF.
Table 11. Channel 2 Circuit Settings
Circuit Parameter Output Voltage, VOUT Reference Voltage, VREF Error Amplifier Transconductance, gm Current-Sense Gain, GCS Switching Frequency, fSW Crossover Frequency, fCROSS Zero Frequency, fZERO Output Inductor, LOUT Output Capacitor, COUT Compensation Resistor, RCOMP Compensation Capacitor, CCOMP Setting Nominal Typical Typical Typical See Step 2 1/12 fSW 1/8 fCROSS Step 3 Step 4 See Equation 18 See Equation 19 Value 1.2 V 0.6 V 550 S 4 A/V 600 kHz 50 kHz 6.25 kHz 2.2 H (47 + 100) F 30 k 820 pF
A schematic of the ADP2116 as configured in the design example described in the Design Example section is shown in Figure 71. Other configurations are shown in Figure 72 to Figure 74. An application circuit of a single interleaved, dual-phase, 6 A output is shown in Figure 72. The schematic in Figure 73 depicts an application circuit with a 3A/2A dual-output load and a 300 kHz switching frequency, and the schematic of a dual-output converter that works at 1.2 MHz with an adjustable VOUT1 and VOUT2 is shown in Figure 74. Table 12 provides the recommended inductor, output capacitor, and compensation component values for a set of popular input and output voltage combinations.
Table 12. Selection Table of L, COUT, and Compensation Values
fSW (kHz) 300 300 300 300 600 600 600 600 600 1200 1200 1200 1200 1200
1
VIN (V) 5 5 5 5 5 5 5 5 5 5 5 5 5 5
VOUT (V) 3.3 2.5 1.8 1.2 3.3 2.5 1.8 1.2 1.2 2.5 1.8 1.2 1.2 0.8
Maximum Load (A) 1 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 6.0 3.0 3.0 3.0 6.0 3.0
L (H) 6.8 5.6 4.7 3.3 3.3 3.3 2.2 2.2 2 x 2.2 1.0 1.0 1.0 2 x 1.0 1.0
COUT (F) 100 122 (22 + 100) 147 (47 + 100) 247 (47 + 2 x 100) 47 69 (22 + 47) 100 147 (47 + 100) 294 (2 x 47 + 2 x 100) 47 57 (10 + 47) 69 (22 + 47) 141 (3 x 47) 122 (22 + 100)
RCOMP (k) 30 27 22 30 33 30 30 30 15 33 33 27 13 33
CCOMP (pF) 1600 1800 2200 1600 750 820 820 820 1600 390 390 470 910 390
A maximum load of 6.0 A is available only with the single interleaved, dual-phase, 6 A output configuration (see Figure 72).
Rev. 0 | Page 31 of 36
ADP2116 APPLICATION CIRCUITS
VIN = 5V 10 100k 1F 100k
22F PGOOD2 VOUT2 = 1.2V, 3A 47F 100F 2.2H
VIN4 VIN5 VIN6 PGOOD2 SW3 SW4 PGND3 PGND4 FB2 V2SET
OPCFG
VDD
EN2
EN1 VIN1 VIN2
22F PGOOD1 3.3H VOUT1 = 2.5V, 3A
VIN3 PGOOD1 SW1 SW2
ADP2116
PGND1 PGND2 FB1 V1SET COMP1 SS1 27k
47F
22F
SYNC
4.7k
SYNC/CLKOUT
FREQ
SCFG GND
30k 820pF
COMP2 SS2 10nF 8.2k
10nF
30k 820pF
fSW = 600kHz
Figure 71. Application Circuit for 3 A/3 A Outputs
VIN = 5V
100k
10 22F 1F 4.7k PGOOD2 V2SET VIN4 VIN5 VIN6 2.2H 47F 100F SW3 SW4 FB2 PGND3 PGND4 COMP2 SYNC/CLKOUT
22F
SCFG
VDD
PGOOD1 V1SET VIN1 VIN2 VIN3
4.7k
PGOOD
ADP2116
SW1 SW2 FB1
2.2H 100F
VOUT = 1.2V, 6A 47F
PGND1 PGND2 COMP1 15k
OPCFG FREQ
VIN
Figure 72. Application Circuit for a Single 6 A Output
Rev. 0 | Page 32 of 36
08436-072
22nF
8.2k
fSW = 600kHz
GND
1.6nF
SS1 SS2 EN1 EN2
08436-071
ADP2116
VIN = 5V 10 100k 1F SCFG VDD EN2 22F PGOOD2 VOUT2 = 3.3V, 2A 6.8H VIN4 VIN5 VIN6 PGOOD2 SW3 SW4 100F PGND3 PGND4 FB2 V2SET SYNC/CLKOUT OPCFG GND COMP2 SS2 FREQ COMP1 SS1 10nF 22k 2.2nF FB1 V1SET 15k EN1 VIN1 VIN2 VIN3 PGOOD1 SW1 SW2 47F 100F 4.7H PGOOD1 VOUT1 = 1.8V, 3A 100k
22F
ADP2116
PGND1 PGND2
CLKOUT
47k
30k 1.6nF
10nF
27k
fSW = 300kHz
Figure 73. Application Circuit for 3 A/2 A Outputs
VIN = 3.3V 10 100k 1F
VDD
100k EN1 VIN1 VIN2 VIN3 PGOOD1 SW1 SW2 1H
12.1k 8.06k
EN2 22F PGOOD2 VOUT2 = 1.4V, 2A
12.1k 16.2k
VIN4 VIN5 VIN6 PGOOD2 SW3
22F PGOOD1 VOUT1 = 1.0V, 3A
ADP2116
1H
SW4 PGND3 PGND4 FB2 V2SET
PGND1 PGND2 FB1 V1SET 82k
47F
100F
82k SYNC 22k 560pF 10nF
OPCFG
FREQ
SCFG
GND
SYNC/CLKOUT COMP1 COMP2 SS1 SS2
10nF
33k 390pF
08436-074
27k
fSW = 1.2MHz
Figure 74. Application Circuit for Adjustable Outputs
Rev. 0 | Page 33 of 36
47k
08436-073
ADP2116 POWER DISSIPATION AND THERMAL CONSIDERATIONS
Power dissipated by the ADP2116 dual switching regulator is a major factor that affects the efficiency of the two dc-to-dc converters. The efficiency is given by Transition losses occur because the P-channel power MOSFET cannot be turned on or off instantaneously. The amount of transition loss is calculated by
Efficiency =
POUT x 100% PIN
(21)
PTRAN = VIN x IOUT x (tRISE + tFALL) x fSW
(26)
where: PIN is the input power. POUT is the output power. The difference between the input power and the output power is the power loss given by
where tRISE and tFALL are the rise time and the fall time of the switching node. In the ADP2116, the rise and fall times of the switching node are in the order of 5 ns. The power dissipated by the regulator increases the die junction temperature, TJ, above the ambient temperature, TA.
TJ = TA + TR
where the temperature rise, TR, is proportional to the power dissipation in the package, PD.
(27)
PLOSS = PIN - POUT
The power loss of the step-down dc-to-dc converter is approximated by
PLOSS = PD + PL
where: PD is the power dissipation on the ADP2116. PL is the inductor power losses. The inductor losses are estimated (without core losses) by
(22)
The proportionality coefficient is defined as the thermal resistance from the junction of the die to the ambient temperature.
TR = JA x PD
(28)
where JA is the junction ambient thermal resistance (34C/W for the JEDEC 1S2P board; see Table 2). (23) When designing an application for a particular ambient temperature range, calculate the expected ADP2116 power dissipation (PD) due to conductive, switching, and transition losses of both channels by using Equation 24, Equation 25, and Equation 26, and estimate the temperature rise by using Equation 27 and Equation 28. The reliable operation of the two converters can be achieved only if the estimated die junction temperature of the ADP2116 (Equation 27) is less than 125C. Therefore, at higher ambient temperatures, reduce the power dissipation of the system. Figure 75 shows the power derating for elevated ambient temperatures at various airflow conditions. The area below the curves is the safe operation area for the ADP2116 dual regulators.
2.2 2.0
MAXIMUM POWER DISSIPATION (W)
PL IOUT x DCRL
2
where: IOUT is the dc load current. DCRL is the inductor series resistance. The ADP2116 power dissipation, PD, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. The power switch conductive losses are due to the output current (IOUT) flowing through the P-channel MOSFET and the N-channel MOSFET power switches that have internal resistance (RDSON). The amount of conductive power loss can be calculated by
PCOND = [RDSON-P x D + RDSON-N x (1 - D)] x IOUT2
where: D is the duty cycle, determined by D = VOUT/VIN. RDSON-P is the internal resistance of the P-channel MOSFET. RDSON-N is the internal resistance of the N-channel MOSFET.
(24)
AIR VELOCITY = 500 LFM 1.8 AIR VELOCITY = 200 LFM 1.6 1.4 1.2 1.0 AIR VELOCITY = 0 LFM 0.8 0.6 0.4 0.2 85 100 115
08436-075
Switching losses are associated with the current drawn by the driver to turn the power of the devices on and off at the switching frequency. The amount of switching power loss is given by
PSW = (CGATE-P + CGATE-N) x VIN2 x fSW
where: CGATE-P is the P-channel MOSFET gate capacitance. CGATE-N is the N-channel MOSFET gate capacitance.
(25)
0 70
AMBIENT TEMPERATURE (C)
Figure 75. Power Dissipation Derating (JEDEC 1S2P Board)
Rev. 0 | Page 34 of 36
ADP2116 CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential for obtaining the best performance from each channel of the ADP2116. Poor circuit layout degrades the output ripple and regulation, as well as the EMI and electromagnetic compatibility performance. For optimum layout, refer to the following guidelines:
*
*
*
*
*
*
Use separate analog and power ground planes. Connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to analog ground. In addition, connect the ground references of power components, such as input and output capacitors, to power ground. Connect both ground planes to the exposed pad of the ADP2116. Place the input capacitor of each channel as close to the VINx pins as possible and connect the other end to the closest power ground plane. For low noise and better transient performance, a filter is recommended between VINx and VDD. Place a 1 F, 10 low-pass input filter between the VDD pin and the VINx pins, as close to the GND pin as possible. Ensure that the high current loop traces are as short and as wide as possible. Make the high current path from CIN through the L, the COUT, and the power ground plane back to CIN as short as possible. To accomplish this, ensure that the input and output capacitors share a common power ground plane. In addition, ensure that the high current path from the PGNDx pin through L and COUT back to the power ground plane is as short as possible by tying the PGNDx pins of the ADP2116 to the PGND plane as close as possible to the input and output capacitors (see Figure 76).
Connect the ADP2116 exposed pad to a large copper plane to maximize its power dissipation capability. Thermal conductivity can be obtained using the method described in JEDEC Standard JESD51-7. Place the feedback resistor divider network as close as possible to the FBx pin to prevent noise pickup. Try to minimize the length of the trace that connects the top of the feedback resistor divider to the output while keeping the trace away from the high current traces and the switching node to avoid noise pickup. To further reduce noise pickup, place an analog ground plane on either side of the FBx trace and ensure that the trace is as short as possible to reduce the parasitic capacitance pickup.
VIN 1F 10 GND GND VDD VINx CIN L COUT VOUT LOAD
ADP2116
SWx
PGNDx
FBx
08436-076
Figure 76. High Current Traces in the PCB Circuit
Rev. 0 | Page 35 of 36
ADP2116 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30
9
0.25 MIN 3.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 77. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP2116ACPZ-R7 2 ADP2116-EVALZ2
1 2
Temperature Range 1 -40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-32-2
011708-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Ordering Quantity 1,500
Operating junction temperature is -40C to +125C. Z = RoHS Compliant Part.
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08436-0-10/09(0)
Rev. 0 | Page 36 of 36

▲Up To Search▲

Price & Availability of ADP2116

	To Download ADP2116 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .